The disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a non-volatile memory device.
A non-volatile memory device is able to retain data even when power is interrupted. Typically, a non-volatile memory device includes gate patterns each having a tunnel isolation layer, a floating gate electrode, a charge blocking layer, and a control gate electrode. A non-volatile memory device stores data by electrically charging/discharging the floating gate electrode. A structure of a typical non-volatile memory device and its problems will be described below with reference to the accompanying drawings.
FIG. 1 is a layout diagram of a typical floating gate type non-volatile memory device.
Referring to FIG. 1, a line-shaped isolation layer formed in a field region 102 defines an active region 101. A bit line is disposed over a substrate in a first direction A-A′, and a word line is disposed in a second direction B-B′ intersecting with the first direction A-A′. A tunnel isolation layer and a floating gate electrode are formed in a certain portion of the active region 101 in the first direction A-A′, and a control gate electrode is formed in the second direction B-B′.
FIGS. 2A, 2B, 3A, 3B, 4A, 4B, 5A, and 5B illustrate a method of fabricating a typical floating gate type non-volatile memory. FIGS. 2A, 3A, 4A and 5A are cross-sectional views taken along the direction A-A′ of FIG. 1, and FIGS. 2B, 3B, 4B and 5B are cross-sectional views taken along the direction B-B′ of FIG. 1.
Referring to FIGS. 2A and 2B, a tunnel isolation layer 210 is formed over a substrate 200. The tunnel isolation layer 210 serves as an energy barrier layer according to charge tunneling, and is formed of oxide.
A conductive layer 220 for a floating gate electrode is formed over the tunnel isolation layer 210. Charges are injected into or discharged from the floating gate electrode. The floating gate electrode is formed of polysilicon. A hard mask layer 230 is formed over the conductive layer 220 for the floating gate electrode. The hard mask layer 230 is formed of nitride.
A device isolation mask pattern 240 extending in the first direction is formed over the hard mask layer 230, and an isolation trench is formed by etching the hard mask layer 230, the conductive layer 220 for the floating gate electrode, the tunnel isolation layer 210, and the substrate 200 by a certain thickness using the device isolation mask pattern 240 as an etch barrier.
Referring to FIGS. 3A and 3B, an isolation layer 250 is formed by burying an oxide layer in an isolation trench. Accordingly, an active region and a field region are defined, and a conductive pattern 220A for a line-type floating gate electrode is formed in the active region. Reference numerals 200A, 210A and 230A represent the etched substrate, the etched tunnel isolation layer, and the etched hard mask, respectively.
The isolation layer 250 is etched to a certain thickness to adjust its effective field oxide height (EFH). The effective field oxide height means a height (W1) from the surface of the substrate 200 in the active region to the surface of the isolation layer 250. The adjusted effective field oxide height increases the area of a floating gate electrode contacting a charge blocking layer, which will be formed in a subsequent process, and thus the coupling ratio of the non-volatile memory device will increase.
Referring to FIGS. 4A and 4B, the hard mask pattern 230A has been removed to expose the surface of the conductive pattern 220A for the floating gate electrode, and a charge blocking layer 260 is formed over the resulting structure. The charge blocking layer 260 prevents charges from passing through the floating gate electrode and moving upward. The charge blocking layer 260 includes an ONO layer in which an oxide layer, a nitride layer, and an oxide layer are stacked.
Referring to FIGS. 5A and 5B, a conductive layer for a control gate electrode is formed over the resulting structure where the charge blocking layer 260 (FIGS. 4A and 4B) is formed. A control gate electrode region defined over the conductive layer for the control gate electrode is exposed, and a control gate mask pattern (not shown) extending in the second direction is formed.
The conductive layer for the control gate electrode, the charge blocking layer, and the conductive pattern 220A for the floating gate electrode are etched using the control gate mask pattern as an etch barrier to thereby form a gate pattern including a tunnel dielectric pattern 210A, a floating gate electrode 220B, a charge blocking layer 260A, and a control gate electrode 270.
During the formation of the gate pattern, the tunnel dielectric pattern 210A may be damaged. This may degrade data retention characteristics and cycling characteristics of the non-volatile memory device, as is described in more detail below.
According to a typical method for fabricating a non-volatile memory device, the conductive layer 220 for the floating gate electrode, which is formed over the resulting structure with the tunnel isolation layer 210, is primarily etched in a line type. During the formation of the gate pattern, the conductive layer 220 is secondarily etched to form an island-shaped floating gate electrode. Accordingly, the tunnel isolation layer 210 may be damaged during the process of etching the conductive layer 270 for the control gate electrode, the charge blocking layer 260, and the conductive layer 220 for the floating gate electrode in order to form the gate pattern.
Meanwhile, it has been proposed to make a recessed floating gate electrode in order to prevent a memory device from being degraded due to the reduction of its channel length that results from the improvement of its integration density.
However, when forming such a recessed floating gate electrode, only its channel length increases while its height is maintained the same, and thus the coupling ratio is decreased. Therefore, the characteristics of the memory device are degraded.